`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/11/07 10:58:03
// Design Name: 
// Module Name: mips
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mips(
	input wire clk,rst,
	output wire[31:0] pcF,
	input wire[31:0] instrF,
	output wire memwriteM,
	output wire[31:0] aluoutM,writedataM,
	input wire[31:0] readdataM 
    );
	
	wire [5:0] opD,functD;
	wire branchD,signextendD;
	wire [4:0] branchopD;
	
	wire regdstE,alusrcE,memtoregE,regwriteE,flushE,alu_unsignE,reg_alu_selE;
	wire [7:0] alucontrolE;	
	wire [3:0] bran_selE;	
	wire jrselE,jalselE,jalrselE;
	wire alustallE;
	
	wire memtoregM,regwriteM;
	wire [1:0] hilowriteM;
	wire jumpM,bran_takeM,pcsrcM;
	wire alustallM;
	
	wire memtoregW,regwriteW,hilo_regW;
	wire [1:0] hilowriteW;
	wire alustallW;

	controller c(
		clk,rst,
		//decode stage
		opD,functD,
		branchopD,
		branchD,
		signextendD,
		
		//execute stage
		flushE,
		memtoregE,alusrcE,
		regdstE,regwriteE,	
		alucontrolE,
        hiloselE,
        reg_alu_selE,
        bran_selE,
        jrselE,jalselE,jalrselE,
        alustallE,
        
		//mem stage
		memtoregM,memwriteM,regwriteM,
		hilowriteM,
		jumpM,
		bran_takeM,
		pcsrcM,
		alustallM,
		
		//write back stage
		memtoregW,regwriteW,
		hilo_regW,hilowriteW,
		alustallW
		);
		
	datapath dp(
		clk,rst,
		//fetch stage
		pcF,
		instrF,
		
		//decode stage
		branchD,
		opD,functD,
		signextendD,
		branchopD,
		
		//execute stage
		memtoregE,
		alusrcE,regdstE,
		regwriteE,
		alucontrolE,
		flushE,
		hiloselE,
		reg_alu_selE,
		bran_selE,
        jrselE,jalselE,jalrselE,
        alustallE,
        
		//mem stage
		memtoregM,
		regwriteM,
		aluoutM,writedataM,
		readdataM,
		hilowriteM,
		jumpM,pcsrcM,
		bran_takeM,
		alustallM,
		
		//writeback stage
		memtoregW,
		regwriteW,
		hilo_regW,
		hilowriteW,
		alustallW
	    );
	
endmodule